Alif Semiconductor /AE722F80F55D5LS_CM55_HE_View /LPUART /UART_LSR

Data Ready This bit is used to indicate that the receiver contains at least one character in the UART_RBR or the receiver FIFO. This bit is cleared when the UART_RBR is read in the Non-FIFO mode, or when the receiver FIFO is empty, in the FIFO mode.

0 (Val_0x0): No data ready

1 (Val_0x1): Data ready

Overrun Error This bit is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the Receiver Shift Register is lost. Reading the UART_LSR or UART_RBR clears this bit.

0 (Val_0x0): No overrun error

1 (Val_0x1): Overrun error

Parity Error This bit is used to indicate the occurrence of a parity error in the receiver if the UART_LCR[PEN] bit is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that this bit will be set if a break interrupt has occurred, as indicated by the BI bit. In this situation, the PE bit is set if parity generation and detection is enabled (UART_LCR[PEN] is set to 1) and the parity is set to odd (UART_LCR[EPS] is set to 0). Reading the UART_LSR or UART_RBR clears this bit.

0 (Val_0x0): No parity error

1 (Val_0x1): Parity error

Framing Error This bit is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid UART_LCR[STOP] bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs the UART will try resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit (data, and/or parity and stop). It should be noted that the UART_LSR[FE] bit will be set if a break interrupt has occurred, as indicated by the BI bit. This happens because the break character implicitly generates a framing error by holding the UART_RX to logic 0 for longer than the duration of a character. Reading the UART_LSR or UART_RBR clears this bit.

0 (Val_0x0): No framing error

1 (Val_0x1): Framing error

Break Interrupt This bit is used to indicate the detection of a break sequence on the serial input data. If in UART mode, it is set whenever the UART_RX is held in a logic 0 state for longer than the sum of start time + data bits + parity + stop bits. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the UART_LSR or UART_RBR clears the BI bit. In the Non-FIFO mode, this bit is set immediately and persists until the UART_LSR is read. Note: If a FIFO is full when a break condition is received, a FIFO overrun occurs. The break condition and all the information associated with it-parity and framing errors-is discarded; any information that a break character was received is lost.

0 (Val_0x0): No break sequence detected

1 (Val_0x1): Break sequence detected

Transmit Holding Register Empty If THRE mode is disabled (UART_IER[PTIME] set to 0) and regardless of FIFOs being enabled or not, this bit indicates that the UART_THR or Tx FIFO is empty. This bit is set whenever data is transferred from the UART_THR or Tx FIFO to the Transmitter Shift Register and no new data has been written to the UART_THR or Tx FIFO. This also causes a THRE interrupt to occur, if the THRE interrupt is enabled. If both modes are active (UART_IER[PTIME] set to 1 and UART_FCR[FIFOE] set to 1, respectively), the functionality is switched to indicate the Tx FIFO is full, and no longer controls THRE interrupts, which are then controlled by the UART_FCR[TET] threshold setting.

0 (Val_0x0): THRE interrupt control is disabled

1 (Val_0x1): THRE interrupt control is enabled

Transmitter Empty This bit is only relevant when FIFOs are enabled (UART_FCR[FIFOE] set to 0). This bit is set whenever the Transmitter Shift Register and the FIFOs are both empty. If the FIFOs are disabled, this bit is set whenever the UART_THR and the Transmitter Shift Register are both empty.

0 (Val_0x0): Transmitter not empty

1 (Val_0x1): Transmitter empty

Rx FIFO Error This bit is only relevant when FIFOs are enabled (UART_FCR[FIFOE] set to 0). This bit is used to indicate if there is at least one parity error, framing error, or break interrupt in the FIFO. This bit is cleared when the UART_LSR is read and the character with the error is at the top of the Rx FIFO and there are no subsequent errors in the FIFO.

0 (Val_0x0): No error in Rx FIFO

1 (Val_0x1): Error in Rx FIFO

Address Received If 9-bit data mode (UART_LCR_EXT[DLS_E] set to 1) is enabled, this bit is used to indicate the 9^th bit of the receive data is set to 1. This bit can also be used to indicate whether the incoming character is address or data. Reading the UART_LSR clears the 9^th bit. Note: Read UART_LSR register before the next address byte arrives. If there is a delay in clearing the interrupt, then software will not be able to distinguish between multiple address related interrupts.

0 (Val_0x0): Indicates the character is data

1 (Val_0x1): Indicates the character is address